By Koen Bertels (auth.), Koen Bertels (eds.)
HW/SW Co-Design for Heterogeneous Multi-Core systems describes the implications and end result of the FP6 undertaking which specializes in the advance of an built-in device chain focusing on a heterogeneous multi center platform comprising of a common goal processor (ARM or powerPC), a DSP (the diopsis) and an FPGA. The software chain takes latest resource code and proposes ameliorations and mappings such that legacy code can simply be ported to a contemporary, multi-core platform. Downloadable software program can be supplied for simulation purposes.
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Lattanzi et al. • additional tools and libraries for format conversion, metrics extractions, interaction with the operating system running on the platform. The hgcc Compiler for the target GPP is extended to support pragma annotations to call the selected HW implementation. The effect of these pragmas is to expand functions into a sequence of Molen APIs (see later). This customized version of the C compiler for the GPP is called hgcc since it is a customization for hArtes (h) of the gcc compiler.
Lattanzi et al. The former ones should be excluded from the parallelism extraction. g. IO or supervisor calls), it shall be marked with a specific directive to be excluded from the partitioning. In this way, a better performing code will be obtained since the parallelism extraction operates only on the data processing region, where no interfacing with external world occurs. For this reason, the source code has to be compliant with this structure to allow the parallelism extractor tool to concentrate its effort on meaningful parts of the application.
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